1. Technical Field
Embodiments relate to a flash memory device, a system including the same, and associated methods.
2. Description of the Related Art
A flash memory device may include a memory cell array, in which a plurality of memory cells serially connected to a single bitline constitute a single string, a plurality of memory cells connected to a single wordline constitute a page, and a plurality of pages constitute a block. In a NAND flash memory device having such a structure, a read operation and a program operation may be performed in units of pages, and an erasure operation may be performed in units of blocks.
A 3D stacked NAND flash memory device may be formed by stacking memory cell arrays in layers. Each of the memory layers may include a plurality of wordlines and a plurality of bitlines. Each memory layer may be connected to a respective row decoder. However, the provision of respective row decoders for each memory layer may increase a chip layout area. In order to reduce a chip layout area, a stacked NAND flash memory device may have many memory layers, e.g., four memory layers, that share a single row decoder. However, since the row decoder is connected to the wordlines of each of the four memory layers, a load on each wordline increases. Accordingly, the Number Of Program operations (NOP) for programming a selected memory cell may increase and, when every program operation which is repeated, a program disturbance may occur in memory cells within a page that are not supposed to be programmed.